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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:03:24 02/29/2012 
-- Design Name: 
-- Module Name:    RegistroPC - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RegistroPC is
    Port ( PC_IN : in  STD_LOGIC_VECTOR (9 downto 0);
           loadEnable : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           PC_OUT : out  STD_LOGIC_VECTOR (9 downto 0));
end RegistroPC;

architecture Behavioral of RegistroPC is

begin
	process (clk)
		begin
			if (rising_edge(clk)) then 
				if (reset = '1' ) then
					--ext hace una extension sin signo
					PC_OUT <= ext ("1", 10);
				elsif loadEnable = '1' then
					PC_OUT <= PC_IN;
				end if;
			end if;
		end process;
end Behavioral;

